Platform-Level Interrupt Controller

The Roa Logic PLIC (Platform Level Interrupt Controller) IP is a fully parameterised soft IP implementing the Interrupt Controller defined in the RISC-V Privileged v1.10 specification

The IP features an AHB-Lite Slave interface, fully compliant with the AMBA 3 AHB-Lite v1.0 specifications.

Bus address and data widths as well as the number of Interrupt Sources and Targets supported are configurable via compile-time parameters. The controller further supports user configurable priority levels and pending events, in addition to interrupt masking via programmable priority thresholds.

PLIC Architecture


  • AHB-Lite Interface with parameterised address and data width
  • User defined number of Interrupt Sources and Targets
  • User defined priority level per Interrupt Source
  • Interrupt masking per target via Priority Threshold support
  • User defined Interrupt Pending queue depth per source

Documentation & Source Code

All source code and documentation is available for download from the Roa Logic GitHub Repository, subject to Licensing Conditions also documented in the repository:

Download from GitHub