Platform-Level Interrupt Controller (PLIC)
Fully parameterised and configurable RISC-V compliant Platform Level Interrupt Controller (PLIC)
AHB-Lite Memory
Fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master.
APB4 GPIO
Fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design
AHB-Lite Timer
Timer module compliant the RISC-V Privileged 1.9.1 specification.